Different Architecture
Von Neumann and Harvard Architecture models
The core elements of today's modern computer devices are consistent with those designed in the dawning phase of technology.
von Neumann described the five subdivisions of a computer system (RICOM)
- Central Arithmetic and Central Control (C): The CPU which executes the instructions
- Main Memory (M)
- Input (I)
- Output (O)
- Recording Medium (R)
Since the data is stored in the same memory unit, which is away from the CPU, it must be fetched into the processor with the help of fetch-decode-execute cycle viz. stored program execution.
Von Neumann Bottleneck: Instructions are data are placed in the same memory unit, which are fetched through the same path viz. the processor can’t simultaneously read instructions and operate on data.
<aside>
👉 Harvard architecture
</aside>
- Unlike Von Neumann Architecture, the data and the instructions are stored in the same memory, in Harvard architecture, both are different
- In modified Harvard architecture, the CPU is accompanied by a small cache, and data memory is different, but instruction memory also contains secondary data.
Flynn’s Taxonomy
Classified on the basis of number of processors, the number of programs they can execute, and the memory structures being used.
<aside>
👉 SISD (Single Instruction Single Data)
</aside>
- A single instruction stream is there, which is made available to the single control unit, so that it can decide what operations need to be performed
- The data the operations need to be performed upon, is taken from the single data stream and made available to the ALU.
<aside>
👉 SIMD (Single Instruction Multiple Data)
</aside>
- There is a single instruction stream which is made available to the single control unit, for instruction decoding.
- There are multiple data streams (shared memory), which based on one-on-one mapping, are made available to the multiple ALUs, all of which perform the same operation on the data.
<aside>
👉 MISD (Multiple Instruction Single Data)
</aside>
There are multiple instruction stream and single data stream viz. multiple streams are there which are made available to multiple control units, and there is a single data stream which is made available to the first ALU, which will operate on the data, and pass it onto the next ALU.
<aside>
👉 MIMD (Multiple Instruction Multiple Data)
</aside>
There are multiple instruction and data streams, which are processed in the control units for instruction decoding, and multiple ALUs operate on multiple data streams.
CPU (Central Processing Unit)
Basics
- A computer is an electro-mechanical device which takes in input, does the processing and produces the output.
- These different components of a CPU are connected to each other with the help of System Bus.
Components of CPU
<aside>
👉 Control Unit
</aside>
Controls the data flow between the components of a computer, and supervises the Fetch-Decode-Execute cycle
<aside>
👉 ALU (Arithmetic Logic Unit)
</aside>
Consists of the Arithmetic Unit (responsible for performing mathematical operations and stuff) and the Logical Unit (responsible for the logical operations (XOR, OR, AND, NOT etc)
<aside>
👉 Registers
</aside>
- These are the smallest data holding elements that are built into processor itself and directly accessible by it, and are used when processing instructions, made with the help of flip-flops.
- They are used to store instructions, values in the CPU that help execute the instructions without having to refer back to the main memory and also the result of those operations
- Storage capacity is very limited viz. on a 64-bit processor, each registrar can hold 64-bits of data, and 32-bits in a 32-bit one, but they are incredibly fast.
<aside>
👉 CPU Clock and Timers
</aside>
- The CPU needs a clock that sends an electric pulse at a regular interval called frequency, which dictates how fast the CPU can execute its internal logic, and is used to synchronise the internal circuitry.
- Timers are implemented due to the fact that a usermode application might take control and never finish whatever it was supposed to do, by getting stuck in an infinite loop, and never return back control to the OS
- A timer is set to interrupt the CPU after a specified period (defined by the OS) after which, the timer interrupts the CPU and control is handed back to the OS.
<aside>
👉 Cache
</aside>
- Caches were designed because without them, a microprocessor would have to sit idle for many cycles until the required data for an operation was taken from the main memory to the registers. To prevent such bottleneck, caches are used
- Cache Coherency is the concept in multi-threading/ multi-processing environment where more than one entity might be looking at a certain information. When that information is updated, it must be updated across all the places it’s stored at, be it the cache, the registers, RAM etc, otherwise problems will occur if obsolete data is in place.
- Built into the processor as well, and they are used to store data proactively pulled from the main memory to enable fast access.
- L1 and L2 level caches are made available individually to all the logical computing cores, and L3 is shared b/w all the cores.
Types of registers